1. Field of the Invention
The present invention relates to a compound semiconductor device and a method of manufacturing the same and, more particularly, a compound semiconductor device having a Schottky gate such as a high electron mobility transistor, a metal semiconductor field effect transistor, etc. and a method of manufacturing the same.
2. Description of the Prior Art
As a compound semiconductor device having a Schottky gate, there have been known a high electron mobility transistor (HEMT), a metal semiconductor field effect transistor (MESFET), and the like.
In such compound semiconductor devices, reduction in an influence of surface states upon a surface depletion layer and control of a threshold voltage of a transistor have been achieved by providing a recessed structure in a compound semiconductor layer which is located in a gate electrode connection portion and its peripheral area.
The field effect transistor employing the recessed structure has been set forth in, e.g., {circle around (1)} IEEE MTT-S Digest (1997) pp 1187-1190, {circle around (2)} IEEE MTT-S Digest (1998) pp 439-442, {circle around (3)} Patent Application Publication (KOKAI) Hei 5-129341, {circle around (4)} Patent Application Publication (KOKAI) Hei 5-251471, {circle around (5)} Patent Application Publication (KOKAI) Hei 9-8283, and the like.
For example, the HEMT set forth in the reference {circle around (1)} has a structure shown in FIG. 1.
In FIG. 1, an undoped AlGaAs buffer layer 102, an n+-AlGaAs first electron supply layer 103, an undoped AlGaAs first spacer layer 104, an undoped InGaAs channel layer 105, an undoped AlGaAs second spacer layer 106, an n+-AlGaAs second electron supply layer 107, an undoped AlGaAs Schottky layer 108, an nxe2x88x92-GaAs intermediate layer (buried layer) 109, and an n+-GaAs cap layer 110 are formed in sequence on a semi-insulating GaAs substrate 101. An AlGaAs layer 111 is formed between the n+-GaAs cap layer 110 and the nxe2x88x92-GaAs intermediate layer 109.
A first recess 112 is formed in the cap layer 110 to expose the intermediate layer 109 in the periphery of a gate region. In addition, a second recess 114 is formed in the intermediate layer 109 to bury a lower portion of a gate electrode 113 made of tungsten silicide (WSi). The first recess 112 and the second recess 114 are formed to adjust a depth of a surface depletion layer.
A gold (Au) layer 115 is connected to the gate electrode 113 to reduce its resistance value.
The cap layer 110 is separated into a source side and a drain side on both sides of the gate electrode 113 by the first recess 112. A source electrode 116s and a drain electrode 116d, both being ohmic-connected to the cap layer 110, are formed on the cap layer 110 which has remained on the source side and the drain side respectively. In this case, a distance L from an edge of the first recess 112 to an edge of the second recess 114 between the drain electrode 116d and the gate electrode 113 is referred to as a recess length hereinafter.
In such HEMT, carriers supplied from the drain electrode 116d come up to the channel layer 105 via the cap layer 110, . . . , the second spacer layer 106, etc. Then, the carriers travel in the channel layer 105 from the lower side of the drain electrode 116d to the lower side of source electrode 116s by the electric field. Then, the carriers come up to the source electrode 116s via the second spacer layer 106, . . . , the cap layer 110. Travel of the carriers in the channel layer 105 can be controlled by a depletion layer which spreads out from the gate electrode 113 when voltage is applied.
By the way, in the HEMT having the above structure, a sufficient gate breakdown voltage has not been able to be achieved since, if the backward bias voltage is applied to the gate electrode 113, a phenomenon that a leakage current is increased gradually with the lapse of application time, i.e., a walk-out phenomenon, is caused.
Moreover, control of the gate forward bias has not been able to be sufficiently performed.
Besides, the fact that, if the recess length is less than 1 xcexcm, a high power added efficiency cannot be maintained has been confirmed according to the experiment done by the inventors of the present invention.
It is an object of the present invention to provide a compound semiconductor device which is capable of improving a breakdown voltage while suppressing generation of a walk-out phenomenon and also maintaining a high power added efficiency even if a recess length in a region between a gate electrode and a cap layer is set to 1 xcexcm or less, and a method of manufacturing the same.
(1) The above problems can be overcome by providing a compound semiconductor device which comprises a channel layer formed on a compound semiconductor substrate, and formed of material which has a first donor concentration and a first bandgap; a carrier supply layer formed on the channel layer, and formed of material which has a second donor concentration being higher than the first donor concentration and a second bandgap being wider than the first bandgap; a first compound semiconductor layer formed on the carrier supply layer, and containing donors in at least one of a lower layer portion and an upper layer portion within a range of impurity concentration of 1xc3x971016 to 1xc3x971017 atoms/cm3; a gate electrode connected to the first compound semiconductor layer; a cap layer formed on the first compound semiconductor layer in a source region and a drain region which arc formed on both sides of the gate electrode, and formed of material which has a third donor concentration being higher than the first donor concentration and a third bandgap being narrower than the second bandgap; a source electrode at least a part of which is formed on the cap layer in the source region; and a drain electrode at least a part of which is formed on the cap layer in the drain region.
According to the compound semiconductor device of the present invention, the first compound semiconductor layer whose donor concentration is set to 1xc3x971016 atoms/cm3 to 1xc3x971017 atoms/cm3 is provided between the cap layer and the carrier supply layer.
According to the donor of such concentration, the holes being separated in the channel layer can be prevented from reaching the surface of the first compound semiconductor layer, whereby contraction of the surface depletion layer can be suppressed and thus generation of the walk-out phenomenon can be prevented.
In this case, since the donor concentration is set to less than 1xc3x971017 atoms/cm3, the situation that the gate breakdown voltage is easily reduced because of high concentration of donor in the first compound semiconductor layer cannot be brought about.
(2) The above problems can be overcome by providing a compound semiconductor device which comprises a channel layer formed on a compound semiconductor substrate, and formed of material which has a first donor concentration and a first bandgap; a carrier supply layer formed on the channel layer, and formed of material which has a second donor concentration being higher than the first donor concentration and a second bandgap being wider than the first bandgap; a Schottky layer formed on the carrier supply layer, and formed of material which has a third bandgap being wider than the second bandgap; a gate electrode connected to the Schottky layer; a buried layer having a recess in which a part of the gate electrode is buried; a cap layer formed on the Schottky layer in a source region and a drain region which are formed on both sides of the gate electrode, and formed of material which has a third donor concentration being higher than the first donor concentration and a fourth bandgap being narrower than the second bandgap; a source electrode at least a part of which is formed on the cap layer in the source region; and a drain electrode at least a part of which is formed on the cap layer in the drain region.
According to the compound semiconductor device of the present invention, the bandgap of the Schottky layer formed on the carrier supply layer is set higher than that of the carrier supply layer.
Therefore, the energy barrier between the gate electrode and the Schottky layer can be enhanced to thus improve the gate breakdown voltage.
However, if the bandgap of the Schottky layer is enhanced, the ohmic resistance of the source/drain regions is increased. Therefore, while suppressing a total film thickness from the Schottky layer to the cap layer, metal constituting the source/drain electrodes and the semiconductor layers therebelow are alloyed by heating, so that such alloy layer can be easily made to reach the electron supply layer. As a result, the ohmic resistance value can be reduced. However, when such film thickness is adjusted, it is not preferable that the thickness is made too thin to such extent that the surface depletion layer comes up to the carrier supply layer since supply of the carriers to two dimensional carrier gas area is decreased.
(3) The above problems can be overcome by providing a method of manufacturing a compound semiconductor device which comprises the steps of forming a channel layer on a semiconductor substrate; forming a carrier supply layer, which supplies carriers to the channel layer, on the channel layer; forming a Schottky semiconductor layer, which has a gate connection region, on the carrier supply layer; forming a gallium-arsenide buried layer on the Schottky semiconductor layer; forming a gallium-arsenide cap layer on the gallium-arsenide buried layer; forming a first recess in a region containing a gate region by etching a part of the gallium-arsenide cap layer; forming a silicon nitride film in the first recess and on the gallium-arsenide buried layer; heating the gallium-arsenide buried layer which is covered with the silicon nitride film; forming an opening portion by selectively etching the silicon nitride film on the gate connection region; forming a second recess by etching the gallium-arsenide buried layer via the opening portion; forming a gate electrode on the gate connection region of the Schottky semiconductor layer via the second recess; forming a source opening portion and a drain opening portion in the gallium-arsenide cap layer on both sides of the first recess by patterning the silicon nitride film; and forming a source electrode in the gallium-arsenide cap layer via the source opening portion and forming a drain electrode in the gallium-arsenide cap layer via the drain opening portion.
Also, the above problems can be overcome by providing a compound semiconductor device which comprises a channel layer formed on a semiconductor substrate; a carrier supply layer formed on the channel layer; a Schottky semiconductor layer formed on the carrier supply layer and having a gate connection region; a gallium-arsenide buried layer formed on the Schottky semiconductor layer; a gallium-arsenide cap layer formed on the gallium-arsenide buried layer; a first recess formed in the gallium-arsenide cap layer to expose a part of the gallium-arsenide buried layer, and having a width which is wider than the gate connection region; a second recess formed in the gallium- arsenide buried layer to expose the gate connection region of the Schottky semiconductor layer; a silicon nitride film provided in the first recess to extend from an end surface of the second recess onto the gallium-arsenide buried layer and the gallium-arsenide cap layer; a gate electrode connected to the Schottky semiconductor layer in the second recess; and a source electrode and a drain electrode formed on the gallium-arsenide cap layer respectively.
Next, an operation of the present invention will be explained.
According to the invention, the GaAs buried layer is heated after the silicon nitride film has been formed on the GaAs buried layer, in which the second recess is formed, in the region located on the inside of the first recess formed in the cap layer. Therefore, even if the gallium oxide layer and the arsenic layer are generated because the surface of the GaAs buried layer is oxidized, such arsenic layer can be discharged into the outside through the silicon nitride film by heating.
The leakage current is made easily flow since conductivity of the arsenic layer is high, so that the three-terminal breakdown voltage (Vdsx) is caused to reduce. Since the arsenic layer disappears substantially by heating, the three-terminal breakdown voltage (Vdsx) between the drain electrode, the gate electrode, and the source electrode can be increased. The power added efficiency can also be improved since the three-terminal breakdown voltage (Vdsx) can be increased.
As a result, it has been evident experimentally that, even if the interval between the first recess and the second recess is set to less than 1 xcexcm, reduction in the power added efficiency can be prevented.
It is preferable that the heating temperature is set in the range of 500 to 700xc2x0 C.